RISC-Processor
RISC stands for 'Reduced Instruction Set Computer', the basic premise of which is as follows: Conventional processors spend most of their time executing only a small subset of simple instructions. By providing only these commonly used instructions and abstaining from complex patterns of memory access, RISC processors can be simpler and hence run faster and more efficiently. The RISC approach on how new High Level Language programs should be compiled and executed efficiently on a processor architecture was implemented by simplifying the instruction set and adapting it to the real requirements of user programs.
The execution characteristics of machine instruction sequences generated from HLL programs can be studied under three main groups:
1) The frequency of operations performed.
2) The types of operands and their frequency of use and
3) Execution sequencing (frequency of jumps, loops, subprogram calls).
It was observed that the frequency distribution of executed machine instructions was: moves- 33%, conditional branch-20%, Arithmetic/logic: 16% and others: Between 0.1% and 10%. Also majority of instructions use simple addressing modes, in which the address can be calculated in a single cycle (register, register indirect, displacement). Complex addressing modes (memory indirect, indexed + indirect, displacement + indexed, stack) are used only by ~18% of the instructions. The majority of operands are local variables of scalar type, which can be stored in registers. Investigations were also performed about the percentage of the total execution time spent executing a certain HLL instruction. It turned out that, most of the time is spent executing CALLs and RETURNs.
Thus the RISC approach was taken with the goal: to create an instruction set containing instructions that execute quickly. RISC processor has three basic levels: 1) All instructions are executed in a single cycle 2) Memory will only be accessed via load and store instructions and 3) All execution units are hardwired with no micro coding. RISC instructions are designed such that they can be executed in a single machine cycle (after fetched and decoded) and operate without the referencing the memory (pipeline operation). Simple RISC instructions results in reduced complexity of the control unit and the data path; as a consequence, the processor works at a high clock frequency. Thus the main features of RISC architectures are: reduced number of simple instructions, few addressing modes, load-store architecture, fixed length instructions and a large number of registers.
